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-- Company: 
-- Engineer: 
-- 
-- Create Date:    15:38:18 04/09/2010 
-- Design Name: 
-- Module Name:    data_out_mux - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity data_out_mux is
    Port ( ena_1 : in  STD_LOGIC;
           ena_2 : in  STD_LOGIC;
           ena_3 : in  STD_LOGIC;
           ena_4 : in  STD_LOGIC;
           wb_data_o : out  STD_LOGIC_VECTOR (31 downto 0);
			  wb_ack_o : out  STD_LOGIC;
			  ack_1 : in  STD_LOGIC;
			  ack_2 : in  STD_LOGIC;
			  ack_3 : in  STD_LOGIC;
			  ack_4 : in  STD_LOGIC;
           data_1 : in  STD_LOGIC_VECTOR (31 downto 0);
           data_2 : in  STD_LOGIC_VECTOR (31 downto 0);
           data_3 : in  STD_LOGIC_VECTOR (31 downto 0);
           data_4 : in  STD_LOGIC_VECTOR (31 downto 0));
end data_out_mux;

architecture Behavioral of data_out_mux is

begin
P1: process(data_1,data_2,data_3,data_4)
begin 

if(ena_1 = '1' and (ena_2 = '0') and (ena_3 = '0') and (ena_4 = '0')) then
wb_data_o  <= data_1;

elsif ((ena_1 = '0') and (ena_2 = '1') and (ena_3 = '0') and (ena_4 = '0')) then
wb_data_o  <= data_2;
elsif ((ena_1 = '0') and (ena_2 = '0') and (ena_3 = '1') and (ena_4 = '0')) then
wb_data_o  <= data_3;
elsif ((ena_1 = '0') and (ena_2 = '0') and (ena_3 = '0') and (ena_4 = '1')) then
wb_data_o  <= data_4;

end if;

end process;

P2: process(ack_1,ack_2,ack_3,ack_4)
begin 

if(ena_1 = '1' and (ena_2 = '0') and (ena_3 = '0') and (ena_4 = '0')) then
wb_ack_o  <= ack_1;
elsif ((ena_1 = '0') and (ena_2 = '1') and (ena_3 = '0') and (ena_4 = '0')) then
wb_ack_o  <= ack_2;
elsif ((ena_1 = '0') and (ena_2 = '0') and (ena_3 = '1') and (ena_4 = '0')) then
wb_ack_o  <= ack_3;
elsif ((ena_1 = '0') and (ena_2 = '0') and (ena_3 = '0') and (ena_4 = '1')) then
wb_ack_o  <= ack_4;
end if;

end process;

end Behavioral;

